1. Field of the Invention
The present invention relates to semiconductor structures and, more particularly, to a semiconductor structure and a method of forming the semiconductor structure with deep trench isolation structures.
2. Description of the Related Art
A metal oxide semiconductor (MOS) transistor is a well-known semiconductor device which can be implemented as either an n-channel (NMOS) device or a p-channel (PMOS) device. A MOS transistor has spaced-apart source and drain regions, which are separated by a channel, and a metal gate that lies over the channel. The metal gate is insulated from the channel by a gate dielectric layer. In addition to metal, the gate of a MOS transistor is also commonly formed with doped polysilicon.
A double-diffused MOS (DMOS) transistor is a power MOS transistor that has a double-diffused well that forms the channel, and a large lightly-doped drain region, known as a drain drift region, which lies between the channel and a heavily-doped drain region. A lateral DMOS (LDMOS) transistor is a DMOS transistor where the source and drain regions are laterally spaced apart. A LDMOS array is a group of LDMOS transistors that are arranged in a pattern, typically as an array of rows and columns.
FIGS. 1A-1B show views that illustrates a conventional LDMOS transistor array 100. FIG. 1A shows a plan view, while FIG. 1B shows a cross-sectional view taken along line 1B-1B of FIG. 1A. As shown in FIGS. 1A-1B, LDMOS transistor array 100 includes a semiconductor structure 110 that has a p-type single-crystal-silicon substrate region 112, and a p-type epitaxial layer 114 that is grown over substrate region 112. In addition, semiconductor structure 110 includes a number of shallow trench isolation structures 116 that are formed in the top surface of epitaxial layer 114 to extend down into epitaxial layer 114.
As further shown in FIGS. 1A-1B, LDMOS transistor array 100 also includes a pair of adjacent LDMOS transistors 120 that are formed in epitaxial layer 114. Each LDMOS transistor 120 includes an n− drain drift region 140 that is formed in epitaxial layer 114, and an n+ drain 142 that is formed in n− drain drift region 140.
In addition, each LDMOS transistor 120 includes a double-diffused well (Dwell) 144 that is formed in epitaxial layer 114. Dwell 144, in turn, includes a p-type region 146 and an n-type region 148 that touches p-type region 146. Each LDMOS transistor 120 further includes an n+ source 150 and a p+ contact region 152 that are formed in epitaxial layer 114. N+ source 150 touches p-type region 146 and n-type region 148. P+ contact region 152, which is laterally surrounded by n+ source 150, touches p-type region 146 and n+ source 150.
P-type region 146, which touches n− drain drift region 140, includes a channel region 154 that lies between n− drain drift region 140 and n-type region 148. P-type region 146, which is spaced apart from n+ drain 142, also has a dopant concentration that is greater than a dopant concentration of epitaxial layer 114. In addition, n+ source 150 lies laterally spaced apart from n+ drain 142. Further, n+ drain 142 touches a shallow trench isolation structure 116, which lies laterally between drain 142 and source 150.
As also shown in FIGS. 1A-1B, each LDMOS transistor 120 includes a gate dielectric structure 160 that touches and lies over channel region 154, and a gate 162 that touches gate dielectric structure 160 and lies over channel region 154. Gate 162 has a square-cornered circular shape. In addition, each LDMOS transistor 120 includes an inner sidewall spacer 164 that touches gate 162, and an outer sidewall spacer 166 that touches and laterally surrounds gate 162.
As further shown in FIGS. 1A-1B, semiconductor structure 110 includes a p-type region 170 that is formed in epitaxial layer 114 between the n− drain drift regions 140 of adjacent LDMOS transistors 120 as a channel stopper. Channel stopper region 170 laterally surrounds each of the LDMOS transistors 120.
In operation, when a first positive voltage, such as 40V, is placed on the n+ drain 142 of a LDMOS transistor 120, and ground is placed on p-type region 146 (by way of the p+ contact region 152) and n+ source region 150, the LDMOS transistor 120 turns off when ground is placed on gate 162. In this case, no electrons flow from n+ source 150 to n+ drain 142.
On the other hand, the LDMOS transistor 120 turns on when a second positive voltage, such as VGS>VTH, is placed on gate 162 while maintaining the remaining bias conditions. In this case, the channel region 154 of p-type region 146 inverts, and electrons flow from n+ source 150 through channel region 154 to n+ drain 142.
One of the problems with LDMOS transistor array 100 is that the LDMOS transistors 120 in LDMOS transistor array 100 require a large amount of lateral separation, and thereby a large amount of silicon real estate, to provide the necessary electrical isolation. For example, 40V isolation typically requires a minimum lateral spacing S of 5.65 um between the n− drain drift regions 140 of adjacent LDMOS transistors 120.
FIGS. 2A-2B show views that illustrate a conventional LDMOS transistor array 200. FIG. 2A shows a plan view, while FIG. 2B shows a cross-sectional view taken along line 2B-2B of FIG. 2A. LDMOS transistor array 200 is similar to LDMOS transistor array 100 and, as a result, utilizes the same reference numerals to designate the structures that are common to both transistor arrays.
As shown in FIGS. 2A-2B, LDMOS transistor array 200 differs from LDMOS transistor array 100 in that LDMOS transistor array 200 utilizes a semiconductor structure 210 in lieu of semiconductor structure 110. Semiconductor structure 210 is the same as semiconductor structure 110 except that semiconductor structure 210 further includes a number of n+ buried layers 211 that are formed in the top portion of substrate region 112 and the bottom portion of epitaxial layer 114.
Semiconductor structure 210 also differs from semiconductor structure 110 in that semiconductor structure 210 includes a number of n-type junction isolation regions 212 that are formed in epitaxial layer 114. Each junction isolation region 212 includes an n+ bottom region 214 that is formed in epitaxial layer 114 to touch and lie above an n+ buried layer 211. Each junction isolation region 212 additionally includes an n− top region 216 that is formed in epitaxial layer 114 to touch and lie above an n+ bottom region 214, and an n+ contact region 218 that is formed in an n− top region 216.
Semiconductor structure 210 further differs from semiconductor structure 110 in that semiconductor structure 210 includes a number of p-type channel stop regions 220 that are formed in epitaxial layer 114. Each channel stop region 220 lies between an n− drain drift region 140 and a junction isolation region 212.
As further shown in FIGS. 2A-2B, semiconductor structure 210 also includes a p-type well region 222 that is formed in epitaxial layer 114 between the n− top regions 216 of adjacent LDMOS transistors 120 as a channel stopper. LDMOS transistor array 200 additionally includes a p+ contact region 224 that is formed in p-type well region 222.
LDMOS transistor array 200 further includes a p− buried region 226 that is formed in substrate 112 and epitaxial layer 114 to lie laterally between adjacent n+ buried layers 211. P− buried region 226, which has a dopant concentration slightly higher than the dopant concentration of p-type substrate 112, is required to minimize the lateral spacing between adjacent n+ buried layers 211.
LDMOS transistor array 200 operates the same as LDMOS transistor array 100, except that each buried layer 211 and junction isolation region 212 of LDMOS transistor array 200 surrounds and junction isolates a portion of epitaxial layer 114 from the remaining portion of epitaxial layer 114. To support 30V operation and below, p− buried region 226 can touch the adjacent n+ buried layers 211 as shown in FIG. 2B. However, to support 40V operation, p− buried region 226 must be laterally spaced apart from the adjacent n+ buried layers 211 due to the junction breakdown limitations between the n+ buried layers 211 and p− buried layer 226.
Like LDMOS transistor array 100, one of the problems with LDMOS transistor array 200 is that a large amount of silicon real estate is required to provide the necessary electrical isolation. When the dopants that were implanted to form the n+ bottom regions 214 are driven in, the n+ bottom regions 214 experience a substantial lateral diffusion of dopants. Thus, there is a need for an LDMOS transistor array that require less silicon real estate.